The present invention relates to integrated circuits and, more particularly, to a circuit and method for adding latency into the address and command signal paths of an integrated circuit memory operating according to the DDR2 standard.
Additive latency is a modification introduced into the DDR2 standard. It is designed to minimize instruction scheduler idles during data transmission to/from the memory. While additive latency is required by the DDR2 standard, known circuits for providing additive latency have serious drawbacks that could impact the performance enhancements provided by the DDR2 standard. These circuits fall into two general categories. A parallel-based circuit and method places too much loading on the eventual output path of the circuit. A series-based circuit minimizes output loading but the circuit and method is too slow. Other drawbacks of known additive latency circuits include variable time delays and changes in performance over time, temperature, and variability due to process conditions.
What is desired is a circuit and method that can provide the additive latency required by the DDR2 standard, yet does not place too much loading on the output of the circuit and is fast enough to be implemented in a DDR2 compliant integrated circuit memory.